Latency
Two different questions. How long the model forward takes, and how quickly the control loop produces an action once its release instant arrives. They are measured at different boundaries and shown in different boxes.
Evaluate vision-language-action inference and CPU control scheduling on the same device, with separate measurements for latency, fidelity and deadlines.
Technical demonstrations and measured records only. No customer deployment is implied.
Each condition has its own boundary and its own result. None stands in for another.
Two different questions. How long the model forward takes, and how quickly the control loop produces an action once its release instant arrives. They are measured at different boundaries and shown in different boxes.
Each action is compared with the full-precision reference output by cosine similarity. That measures how closely the policy output is preserved. It is not task success and is never presented as such.
Missed releases are counted over a stated number of cycles, with the scheduler, core isolation and kernel recorded. A cadence such as 50 Hz or 1 kHz is a cadence we measured, not a current product guarantee.
Measured records where they exist. Where a configuration has not been measured, the box says so.
Not measured for this configuration
The published robotics measurements on this site are for compact control policies, not a vision-language-action model. We do not substitute one for the other.
Engine latency in microseconds: from the expected release instant to action-ready, taken inside the runtime with the monotonic clock. Compact control policy on the CPU loop.
| Scenario | p50 µs | p99.9 µs | max µs | jitter p99.9 µs | Deadline misses |
|---|---|---|---|---|---|
| 50 Hz control (idle) | 21 | 27 | 31 | 0 | 0 |
| 50 Hz + full CPU saturation | 22 | 41 | 45 | ≤3 | 0 |
| 1 kHz torque-rate control | 21 | 24 | 29 | 0 | 0 / 20,000 |
Jetson AGX Orin 64 GB, 12× Arm Cortex-A78AE, L4T R36.4.3, Linux 5.15 stock (PREEMPT, not real-time), clocks pinned, one CPU core isolated, SCHED_FIFO with locked memory and absolute-time periodic release.
Not measured for this configuration
System latency from sensor callback to actuator is a separate, larger boundary. It is never conflated with engine latency, and no full measurement is published here.
0 / 180,000 missed deadlines at 50 Hz and 0 / 3,600,000 at 1 kHz over one hour each. Response p99.9 / max: 26 / 45 µs at 50 Hz, 21 / 36 µs at 1 kHz. Average / peak CPU power at 50 Hz: 2.4 / 3.2 W.
A raw-timestamp verifier outside the engine recomputed the counts. Core isolation was required: without it, rare kernel-interference events produced occasional multi-millisecond stalls. This describes one measured run, not a guarantee.
Cosine similarity to the full-precision reference across four compact control policies: 0.99978 to 0.99999.
This is output similarity, not task success.
Not measured for this configuration
No task-suite result is published. Any future success figure will show numerator and denominator with the checkpoint and task split.
Not measured for this configuration
The measurements above are control-loop runs. A combined run with a VLA policy active on the GPU is the configuration an evaluation would measure.
A self-contained runtime generated by VEIZIK’s own compiler, with a per-device activation. It runs the policy and reports latency and action fidelity from the command line.
Sensors, actuators, the robot’s own safety systems, the real-time kernel choice and the system-level integration. Whole-robot safety is outside what VEIZIK measures or claims.
Figures come from one board class (Jetson AGX Orin) on a stock kernel. They are not a head-to-head comparison with results published on other devices.
Robotics evaluations weigh what else shares the GPU. The Jetson AGX Orin that schedules your control loop also runs the full image stack natively — these were drawn on it.





Shown as what the engine draws on the board — output, not a benchmark; no latency or throughput figure is attached to these images. Each is a FLUX.1-schnell image rendered natively by Veizik on a Jetson AGX Orin, the same class of board that schedules a control loop.
A technical evaluation starts from the inputs below.